Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to a semiconductor device package structure that provides a high breakdown voltage and low parasitic inductance.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. One common power semiconductor device is a high voltage power semiconductor diode. A high voltage power semiconductor diode operates on similar principles to its low-power counterpart, but is able to carry a larger amount of current and typically is able to support a larger reverse-bias voltage in the off-state. In use, high voltage power semiconductor diodes are connected to an external circuit by way of a power overlay (POL) packaging and interconnect system, with the POL package also providing a way to remove the heat generated by the diode and protect the diode from the external environment.
In order to operate efficiently, semiconductor diodes require dielectric isolation between their anode and cathode junction as well as a low loop inductance between the anode and cathode. With respect to providing dielectric isolation between the anode and cathode junction, a high dielectric material that is capable of providing a high reverse breakdown voltage (e.g., up to 10 kV) is typically provided for the semiconductor diode. However, such dielectric materials often have an increased thickness that may be incompatible with certain POL packaging techniques for the semiconductor diode and, if the thickness is not properly controlled, can lead to increased parasitic inductance. With respect to providing a low loop inductance between the anode and cathode, challenges arise with controlling the inductance when using conventional packaging technologies. That is, inherent to conventional packaging technologies are problems associated with the high parasitic inductance of such packages, with this inductance limiting the operating frequency of the semiconductor diode, as it generates losses in the diode during commutation.
To provide dielectric isolation between the anode and cathode junction, it is thus desired that the semiconductor diode include a high dielectric material that is capable of providing a high reverse breakdown voltage, while being compatible with optimal POL packages and packaging techniques and not having a negative effect on the package inductance. To provide low loop inductance between the anode and cathode, it is desired that the POL package for the semiconductor diode be constructed so as to minimize parasitic inductance. The POL package should also provide repeatability and matching of inductances and capacitances between multiple diodes for purposes of constructing diode arrays.
Accordingly there is a need for a semiconductor diode package that provides for a high breakdown voltage in the diode as well as low parasitic inductance in the semiconductor diode package.